1. Field of the Invention
The invention relates to a method for manufacturing a gallium nitride-based III-V group compound semiconductor device.
2. Description of the Related Art
Since epitaxial layers of III-V group nitride such as gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN) were first grown successfully, they have become promising materials for use in high temperature/high power electronic devices and opotoelectronic devices, due to their high direct band gap, high saturation drift velocity, high breakdown field, and chemical inertness. Recent improvements in crystal quality of epitaxial layers with increased dopant concentrations have led to high quality laser diodes, light-emitting diodes, photodetectors, and microwave field effect transistors having been developed based on these epitaxial III-V group nitride structures.
In general, the performance of III-V group nitride device has been limited by contact resistance. Therefore, a key technology in achieving higher performance for III-V group nitride devices is the realization of more reliable metal contacts. Although a wide variety of metals used as contacts with GaN have been reported, the metallic titanium/aluminum (Ti/Al) bilayer has been most widely used as a conventional ohmic contact for n-type GaN. However, such a Ti/Al bilayer is prone to oxidation, which in turn leads to high ohmic resistance during the fabrication process and during operation.
To avoid the oxidation propensity at elevated temperatures, a low resistivity gold (Au) layer should be effective for passivating the Ti/Al bilayer. However, gold would interdiffuse and penetrate into the GaN semiconductor layer, causing deterioration in thermal stability, and ohmic contact property of the semiconductor device.
FIG. 1 is a cross-sectional view showing a typical structure of a GaN-based III-V group compound semiconductor light-emitting device (LED) 100.
As shown in FIG. 1, an LED 100 includes an insulated substrate 1 made of such as sapphire. The substrate 1 has a first major surface 1a and a second major surface 1b. A GaN buffer layer 2 is formed on the first major surface 1a of the substrate 1. An n-type GaN-based III-V group compound semiconductor layer 3 is formed on the buffer layer 2. The n-type semiconductor layer 3 is doped by n-type dopants such as germanium (Ge), selenium (Se), sulfur (S), or tellurium (Te). In addition, the n-type semiconductor layer 3 can be doped by silicon (Si).
An n-type AlGaN layer 4 is formed on the n-type semiconductor layer 3. An active layer 5 is formed on the n-type AlGaN layer 4, and the active layer 5 has a multiple quantum well (MQW) structure, a single quantum well (SQW) structure, or a double-heterostructure (DH) made of such as InGaN/GaN. A p-type AlGaN layer 6 is formed on the active layer 5. The p-type AlGaN layer 6 is doped with p-type dopants such as beryllium (Be), strontium (Sr), barium (Ba), zinc (Zn), or magnesium.
A p-type GaN-based III-V group compound semiconductor layer 7 is formed on the p-type AlGaN layer 6. The p-type semiconductor layer 7 is doped with p-type dopants such as beryllium, strontium, barium, zinc, or magnesium.
As shown in FIG. 1, the LED 100 includes an electrode 8A formed on the n-type semiconductor layer 3 and an electrode 8B formed on the p-type semiconductor layer 7. Conventionally, the electrode 8A includes a metal such as titanium, aluminum, or gold as mentioned above. The electrode 8B is a kind of ohmic electrode, it includes a metal such as nickel (Ni), chromium (Cr), gold or platinum.
Referring to FIG. 2, the flow chart shows conventional steps for manufacturing a light-emitting device 100.
First, as shown in step 201, a buffer layer 2, an n-type semiconductor layer 3, an n-type AlGaN layer 4, an active layer 5, a p-type AlGaN layer 6, and a p-type semiconductor layer 7 are formed on a substrate 1 in this order.
Next, as shown in step 202, a thermal process is performed to activate the p-type AlGaN layer 6 and the p-type semiconductor layer 7. Since doped magnesium atoms in the p-type AlGaN layer 6 and p-type semiconductor layer 7 form Mgxe2x80x94H bonds, holes are not provided. The thermal process is to break the Mgxe2x80x94H bonds and activate the p-type AlGaN layer 6 and p-type semiconductor layer. 7. The thermal process is performed at a temperature ranging from 650 to 780xc2x0 C. for 15 to 60 minutes.
Then, as shown in step 203, the p-type semiconductor layer 7, p-type AlGaN layer 6, active layer 5, and n-type AlGaN layer 4 are partially etched away to expose a surface of the n-type semiconductor layer 3. Here, a part of the n-type semiconductor layer 3 is also etched away.
Next, as shown in step 204, electrodes 8A and 8B are formed, wherein the electrode 8A is formed on the n-type semiconductor layer 3, and the electrode 8B is formed on the p-type semiconductor layer 7. The electrodes 8A and 8B can be formed by known deposition methods such as evaporation or sputtering.
Next, as shown in step 205, an annealing process is performed. The object of this step is to lower the ohmic contact resistance of the electrodes 8A and 8B. The annealing process is generally performed at a temperature ranging from 300 to 600xc2x0 C.
It should be noted that besides forming the electrodes 8A and 8B at the same time as mentioned in step 204, it can also be first forming the electrode 8A, and after the annealing process, forming the electrode 8B.
The invention provides a method for manufacturing a gallium nitride-based III-V group compound semiconductor device, includes the following steps: providing a substrate having a first and a second major surfaces; forming a semiconductor stacked structure over the first major surface of the substrate, wherein the semiconductor stacked structure includes an n-type gallium nitride-based III-V group compound semiconductor layer, an active layer, and a p-type gallium nitride-based III-V group compound semiconductor layer; etching the semiconductor stacked structure to expose a part of the n-type semiconductor layer; forming a first electrode on the n-type semiconductor layer, wherein the first electrode includes an ohmic contact layer, a barrier layer over the ohmic contact layer, and a pad layer over the barrier layer; and performing an annealing process for lowering the contact resistance between the first electrode and the n-type semiconductor layer, and activating the p-type semiconductor layer simultaneously; and forming a second electrode on the p-type semiconductor layer.
A gallium nitride-based III-V group compound semiconductor device in accordance with an embodiment of the invention includes an n-type gallium nitride-based III-V group compound semiconductor layer; and an electrode on the n-type gallium nitride-based III-V group compound semiconductor layer, and the electrode includes an ohmic contact layer, a barrier layer over the ohmic contact layer, and a pad layer over the barrier layer.
A gallium nitride-based III-V group compound semiconductor device in accordance with another embodiment of the invention includes a substrate having a first and a second major surfaces; a semiconductor stacked structure formed over the first major surface of the substrate and which includes an n-type gallium nitride-based III-V group compound semiconductor layer, an active layer, and a p-type gallium nitride-based III-V group compound semiconductor layer; a first electrode on the n-type semiconductor layer and which includes an ohmic contact layer, a barrier layer over the ohmic contact layer, and a pad layer over the barrier layer; and a second electrode on the p-type semiconductor layer.
The ohmic contact of the n-type GaN of the invention has thermal stability endurance much better than that of a conventional Ti/Al/Au multilayer. Therefore, the method for manufacturing the compound semiconductor device of the invention is simpler than the conventional method, and can thus lower the costs and increase the yield.